Many of currently widespread information processing apparatuses are provided with an I/O bus (for example, PCI bus). With increase in speed of data processing in the I/O bus and increase in an amount of data to be handled, a technique of new I/O bus standards is proposed in place of conventional I/O bus standards. For example, as in JP 2007-219873A, a technique of an I/O bus system is known which is designed according to the new I/O bus standards.
FIG. 1 is a block diagram showing a configuration of the I/O bus system described in JP 2007-219873A. This I/O bus system includes hosts 101, a PCI express switch 105, and I/Os 103.
The host 101 includes a CPU 111, a memory 113, and a route complex 112. The route complex 112 connects the CPU 111, the memory 113, and the PCI express switch 105. A use right of the I/O 103 is assigned to any one of the hosts 101. The assignment of the I/O 103 to the host 101 can be changed.
The PCI express switch 105 includes upstream PCI express-network bridges 121, a network switch 122, downstream PCI express-network bridges 125, and a system manager 151. The upstream PCI express-network bridges 121 bridge between a PCI express bus and a network on the side of the host 101. The network switch 122 transfers network packets. The downstream PCI express-network bridges 125 bridge between the network and the PCI express bus on the side of I/O 103. The system manager 151 controls connection between the upstream PCI express-network bridge 121 and the downstream PCI express-network bridge 125, and sets assignment of the I/O 103 to the host 101.
The upstream PCI express-network bridges 121 are connected to a plurality of downstream PCI express-network bridges 125. The upstream PCI express-network bridge 121 receives I/O packets destined to the I/O 103 from the route complex 112, and encapsulates the received I/O packet to a network packet and transfers it to the network switch 122. At this time, the upstream PCI express-network bridge 121 writes as a destination of the encapsulated packet, a network address of the downstream PCI express-network bridge 125 connected to the I/O 103 as a destination of the I/O packet before encapsulation.
Moreover, the upstream PCI express-network bridge 121 receives a network packet obtained by encapsulating an I/O packet destined to the host 101 from the network switch 122. The upstream PCI express-network bridge 121 performs decapsulation of the received network packet and transmits the obtained packet to the route complex 112.
The downstream PCI express-network bridge 125 is connected to one of the upstream PCI express-network bridges 121. The downstream PCI express-network bridge 125 receives from the I/O 103, an I/O packet destined to the host 101 corresponding to the upstream PCI express-network bridge 121 connected to this downstream PCI express-network bridge 125, encapsulates the received I/O packet to a network packet, writes in a destination of the encapsulated packet, a network address of the upstream PCI express-network bridge 121 connected with the host 101 to which the I/O packet is destined, and transfers it to the network switch 122. Moreover, the downstream PCI express-network bridge 125 receives a network packet obtained by encapsulating an I/O packet destined to the I/O 103 from the network switch 122, decapsulates the network packet to obtain the I/O packet, and transmits the I/O packet to the I/O 103.
FIG. 2 is a diagram showing an address space 115-1 of the host 101-1. A case that all the I/O 103-1 to I/O 103-M are assigned to the host 101-1 will be described. The address space 115 of the host 101 includes an ID number space 1151 as a space for ID numbers including a group of three numbers (a bus number, a device number, and a function number); and a physical memory space 1152. The addresses of the I/Os 103 used by the host 101 are mapped into the ID number space 1151 and the physical memory space 1152. Here, the I/O 103-1 to I/O 103-M are respectively mapped into maps 1511-1 to 1511-M for the I/O 103-1 to I/O 103-M in the ID number space 1151-1 and maps 1521-1 to 1521-M for the I/O 103-1 to I/O 103-M in the physical memory space 1152-1.
The conventional I/O bus system having such a configuration operates as follows. The system manager 151 transmits a control packet to the downstream PCI express-network bridge 125 to control to which of the upstream PCI express-network bridges 121 the downstream PCI express-network bridge 125 is connected. The I/O 103 is assigned to the host 101 connected to the upstream PCI express-network bridge 121 connected to the downstream PCI express-network bridge 125.
The upstream PCI express-network bridge 121 and the downstream PCI express-network bridge 125 encapsulate the I/O packet transmitted and received between the host 101 and the I/O 103 assigned to the host 101 into the network packet, and tunnels between the upstream PCI express-network bridge 121 and the downstream PCI express-network bridge 125.
The host 101 recognizes that the upstream PCI express-network bridge 121 is an upstream PCI-PCI bridge inside a standard-based PCI express switch and that the downstream PCI express-network bridge 125 is a downstream PCI-PCI bridge inside the PCI express switch, thereby recognizing that a region between the upstream PCI express-network bridge 25 and the downstream PCI express-network bridge 21 is under the standard-based PCI express switch. Thus, without requiring special software for the host 101, the conventional I/O bus system can freely change the assignment of the I/O 103 to the host 101.